1. Field of the Invention
The present invention relates to an adaptive equalizer for use with a clock and data recovery (CDR) circuit of a serial communication link.
2. Description of the Related Arts
Serial communication links, such as HDMI (High-Definition Multimedia Interface), DVI (Digital Video Interface), UDI (Unified Display Interface), PCI-Express, Fiber Channel, Ethernet, etc., are widely used to transmit digital data from a transmitter to a receiver over a physical cable. For example, HDMI communication links transmit digital video and audio data from the transmitter to the receiver over a physical cable, and typically use a CDR circuit at the receiver to recover the differential NRZ (Non-Return to Zero) data and clock signals transmitted from the transmitter. Because the physical cable often exhibits the characteristics of a low-pass filter, the NRZ data received at the receiver for recovery by the CDR circuit typically have different amplitudes depending upon the frequency, which causes noise to be present in the recovered NRZ data.
Equalizers have been used with the CDR circuit to compensate for the different amplitudes of the NRZ data depending upon the frequency. Conventional equalizers attempt to equalize the NRZ data received at the receiver by equalizing the amplitudes at different frequencies of the NRZ data. Most conventional adaptive equalizers use an analog comparator or a digital comparator combined with an analog-to-digital converter (ADC) to examine the eye diagram of the NRZ data. However, such conventional equalizers require very complicated circuitry to implement, require a lot of hardware resources, and still fail to effectively remove jitter caused by timing misalignment and dispersion of the NRZ data depending upon the different frequencies of the NRZ data.
Therefore, there is a need for an equalizer that can remove effectively jitter in the different frequencies of the NRZ data. There is also a need for an equalizer that can be implemented with simple circuitry.